1. PLL & SerDes IP design supporting & verification
2. Next generation low power SerDes design
3. PLL supporting

職缺需求

1. Master or above with major in EE or Telecommunication Engineering related field.
2. Familiar with analog circuit design and verification.
3. At least 2 years work experiment on PLL & SerDes .
4. Excellent working attitude and good interpersonal and communication skills.