1.The verification and simulation on Wireless Connectivity chip development, Validation and debugging of function block and system level RTL design with system verilog and verilog
2.Function block and system architecture’s RTL simulation
3.FPGA validation and ASIC implementation of Function block and system architecture
4.Cowork with design engineer to develop automatic and randomized testbench with advanced coverage
5.Achieve system level verification through teamwork with design engineer, systems architecture engineer and communication protocol engineer
6.Take over function block RTL design, and responsible for the design maintainance and modification of later projects

職缺需求

1. Familar with Verilog & ASIC Design flow
2. Familar with FPGA & ASIC verfication flow
3. Familar with wireless communication system
4. Familar with WiFi, Bluetooth , GPS system
5. Familar with Perl , Matlab, TCL, C, C++ , System Verilog, System is an plus