Staff Analog Modeling Engineer

Location: Shanghai, China

Scope and responsibility:

• Communicate with analog designer to understand the circuit function.

• Model analog circuit function with System Verilog NET Type.

• Setup block level mix signal simulation bench

• Do mix-signal simulation and spice simulation to ensure the model and schematic function consistence.

• Support verification engineer for mix signal verification in chip level.

• Extra bandwidth will involve into verification work of test case, reference model and environment development.

Education，Experience, Preferred Skills & Knowledge:

• MS in EE/CS/ME.

• Minimum of 5 years’ experience.

• Candidate should be familiar with basic analog and digital circuit like OSC,I/O,ADC,DAC.

• Candidate should be familiar with System Verilog and Verilog HDL.

• Additional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.

• Candidate should be familiar with industry standard ASIC design and verification tools and flow.

• Good knowledge of UVM verification methodology would be added advantage.

• Good knowledge of DDR or HSS basic circuit would be added advantage.

• Good knowledge of Python and shell programming would be an added advantage.

• Independent and self-managing.

上班地址：桂箐路65号新研大厦B幢12楼