Responsibilities

• Work with project leader closely to finish device architecture design
• Work with System Engineer closely and provide input to the writing of System Functional Specifications of the products, i.e. be an active part in the early design phase of a product
• Write both module level and device level specifications in English
• Develop synthesizable RTL using System Verilog per module/device specification
• Documentation for related tasks, also be responsible for document review, code inspection and other tasks required by quality process
• Work with hardware and software engineers in the integration of FPGA

Requirements

• Bachelor Degree in Electrical & Telecommunication
• Minimum 3 years working experiences on FPGA or ASIC design
• Familiar with FPGA design tools: Mentor Questa, Xilinx ISE/Vivado, Altera Quartus, etc.
• Good experience on Packet Processor/Processing and Traffic Management(TM), MAC Interface design, Embedded Processor/CPU field, etc.
• Familiar with Network Processor architecture/implementation
• Broad knowledge base of telecommunication industry
• Ability to produce consistent quality under pressure

上班地址：深圳市南山区海德二道茂业时代广场18楼