工作职责:

1. We are looking for talented and experienced individuals who are self-motivated, having good communication skills, and eagle to learn and grow in SOC design and synthesis areas.

2. Candidates will work closely with FE design engineers to understand the design and produce spec requirements and constraints.

3. Candidates will perform synthesis, STA, UPF, Dfx and related design steps/flows to produce quality netlist and design for downstream APR work.

4. Senior leads/engineers will also involve in developing methodology in automation and QA flow to ensure design quality. Synthesis engineers are expected to be familiar with C/C++, TCL/Shell programing language.

5. Candidates with experiences or are familiar with FE design flow and APR design flow will be a big plus.

任职资格:

1. EE/CS related major, bachelor degree or above;

2. More than 10 years working experience in related fields.

上班地址：海宁