Who we are?

ESIP develops and delivers High Speed networking and communication IPs (such as Ethernet PHY, PCIE, USB-TypeC, DP/HDMI) to all Intel devices (Client and Servers CPU’s / Chipset / Controllers).

We are looking for an experienced PHY System Algo Engineer to join the best in the world Serdes design team.

This team develops DSP algorithms simulation using advanced simulation tools, while performing basic tradeoffs: power die size performance.

HW implementation coding, validation and synthesis. Lab Validation (SV) basic abilities.

#WEAREIPG

• IMPORTANT:  Please be informed that Intel is proactively trying to find candidates for a SERDES PHY system/architect position which is frequently available at Intel.  Please note that the position may not be available at this time. If you would be interested in this position should it become available, we would encourage you to apply, and our hiring team will be glad to contact you when/if relevant.”

Qualifications

• M.Sc or higher in Electrical engineering, with study fields: VLSI, Mixed-signal/Analog, Signal processing.

• Familiarity with PHY architectures for HSIO/SERDES systems, with emphasis on Ethernet standards, PCIe, USB, TB, etc'

• 5+ years of experience and knowledge in at least two or more of the following fields: DSP, system identification, modeling, top-down design, signal integrity, mixed-signal subsystems, high speed ADC 5Gsps, Firmware/real time.

• 3+ years of experience with at least three of the following tools/languages: Matlab, Simulink, Python, Verilog, C++, JMP

• Experience in lab work for design validation basic equipment operation, scripting for test automation, data analysis and post processing, etc. Basic understanding of analog / mixed-signal circuits high level is a must.

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Other Locations
Israel, Petah-Tikva;