1. SoC/ASIC & package architecture design for high performance computing with High bandwidth Memory (Server, Networking, AI, AR…etc) applications.

2. Execute SI/PI/RF/EMI validation for the system requirements on eye diagram, jitter, latency, IR drop, cross-talk, and SSN specs from chip to PCB.

3. Develop system integration design and requirement based on SiP, PoP, PiP, Chip stacking, and other 3DIC technologies.

4. Working with marketing/technology team on technology competitive analysis and develop package technology road map for future products requirements.

1. Ph.D. in electrical engineering or communication engineering

2. Min 3+ years working experience in SoC/NoC & package/integration co-design for high performance computing products.

3. SoC/ASIC architecture & package knowledge and understanding of trade-offs made for partitioning of the key devices (AP, SoC, NoC, GPU, CPU...)

4. Excellent written and spoken communication skills in English is required

5. Hands-on participation and a strong sense of ownership is required

6. Strong technical problem-solving and analytical skills, based upon fundamental, rather than empirical models is required