AlderLake with hybrid architecture is on the way and were already developing the next generation Intels CPUCore and Client Development Group is responsible to full RTL2GDSII flow Synthesis floor planning placement CTS route post route optimization extraction static timing physical verification EMIR and ECO flowsWere looking for a BackEnd Lead to manage plan and mentor a team of talented engineers to execute teams RTL2GDSII flow activities

Qualifications

At least 10 years of professional experience in complex backend design at IP or SoC level Experience Place Route tools like Synopsys DCT ICC PrimeTime and Cadence Innovus Conformal Must have good understanding of timing analysis including noise and signal integrity power analysis physical verification formal verification Scripting skills to debug flow related issues and make enhancements as appropriate Previous Team leading or managerial experience is a must Great interpersonal communication skills Problem solving skills C2DG_IL

Inside this Business Group

The Silicon Engineering Group is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.