Job Description: IPG is charted to provide Mixed Signal IPs like GPIO, Digital Thermal Sensor, View-pin, Die-2-Die interface for Intel SOC products in the space of Client, Graphics, Data Centre GPIO Circuit Design lead is responsible for low power and reliable GPIO analog circuit Design and corresponding Sign-off Verification Functional, reliability, Mixed-Signal Verification. Objectives of the position Own and deliver the Circuit Design and Sign-off verification of GPIO IPs. Groom the junior team members towards technical excellence, drive innovation in the team and harvest publications and patents. Work with internal stakeholders such as mask design for circuit implementation and logic design to design the analog and digital interface Continuously drive the Turnaround time, robustness of circuit design and area and power of GPIO IPs. Drive Post-silicon electrical validation, post silicon debug and high volume manufacturing support for the IPs. Desired Competencies and Experiences: Deep understanding of Circuit design and physical design of Analog Designs on advanced process technologies. Expertise on analog design blocks like GPIO, Differential Tx and Rx, voltage and current references, oscillators, ESD. Good grasp on Industry standard tools such as Cadence design Environment ADEXL or Virtuoso Knowledge of DRC, LVS, and post layout extraction tools Familiarity with RTL behavioral coding and simulations, timing extractions of custom blocks Fast learner, good problem solving skills, multitasking ability and attention to quality and detail.

Qualifications

BS or MS - EE and 8+ Years of industry experience.

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

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