职位描述：
1.灵活运用现有的DV工具完成ASIC/SOC设计
2.独立运用工具完成大量的DV工作
3.为新的设计、块级和芯片级测试计划的创建和实现、覆盖率分析和回归清理在DV环境中移植/创建。

任职要求：
1.具备良好的验证方法知识，如VMM,OVM
2.具有丰富的仿真模型创建和测试平台构建经验
3.较强的RTL编程能力，熟悉前端设计流程
4.较强的C/ c++软件开发经验
5.熟悉Perl、C shell、Makefile等脚本语言

Requirements:
The candidate should have good understanding on ASIC/SOC design flow and should have:
Good knowledge of design verification methodology, such as VMM or OVM.
Many experiences with simulation model creation and the testbench build
Strong RTL coding with Verilog and familiar with front-end design flow
Strong C/C++ software development experiences
Be familiar with scripting language, such as Perl, C shell, Makefile.
It is a plus if the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; SSIC/HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, Universal Flash Storage, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.
Hands-on lab experience is another plus, able to understand and/or use the use scopes, logic analyzers, has knowledge or skill of board-level lab debugging.
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, imaginative thinking and sophisticated analytical techniques, self-driven for quality and timely result, capability to solve complex problems and makes some modifications to standard methods and decision-making on important.

Responsibility:
The successful candidate will apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market for ASIC/SOC design. He/She should be able to work independently on various DV tasks and providing technical guidance to the DV team. The candidate would involve technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup.

上班地址：张江高科技园