ESIP develops and delivers PLL's and all High Speed SerDes's to Intel devices.

Team delivers state of the art technologies as 112G and higher Ethernet SerDes.

This position is for a student at an Analog Circuit Design group that is in the front of the technology - both from the process perspective, and from the complexity and leading edge design activities. The group designs Phase Locking Loops (PLLs) and delivers PLL systems to other Intel teams. The student will take part in the various activities that are done within the team. The activities range from design, validation and integration of the building blocks, analysis and validation on to the PLL system and wrapping up and delivering the hard-IP to other design teams. Post manufacturing verification and debugging is also done by the PLL team.
The position will be an integral part of the development team. The work is done in a small and excellent team.

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Qualifications

• Students for Bachelor, Master or PHD at Electrical Engineering.
• At least 1.5 years of remaining studies
• Available to work at least 20 hours a week

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.