1.Create and review design and verification documentation
2.Design and verify digital logic in Verilog RTL
3.Plan and track design tasks to meet the targets at the planned time
4.Close cooperation and interaction with international teams

職缺需求

1.Master Degree in Microelectronics/EE/CS/relevant
2.2+ years experience on digital design and verification with Verilog RTL.
3.Knowledge of digital synthesis and DFT.
4.Good communication skills.
5.Good script programming abilities on perl and unix scripting.
6.Good verbal and written skills, English and Chinese.
7.One or more of the following skills or experiences is a plus,
a.Strong knowledge of ARM/DSP, AXI/AHB/APB bus.
b.Proficient in building verification environments, using SystemVerilog(UVM, OVM, VMM).
c.Experience of mix-signal design.
d.Experience of wireless communication design.
e.Experience of FPGA, board level debug.
f.Experience of integration job.