Intel's Serdes IP design team is looking for experienced Backend Engineer to join the best in the world Serdes design team.

This team had many firsts in this area of design and our customer base is expanding rapidly.

Some of our publicly announced products includes the Ethernet PHY design for 5 G base station.

Another IP is the First 116 Gbps OIF/.CEI Serdes (Google "Intel 116Gbps Test Chip Demo v2").

Oversees Design and implementation of digital partitions from RTL to GDSII. Candidate will also will perform full validation including all timing checks, LV checks, FV, Power analysis and Reliability validation. Candidate will colaborate with logic design team , DFX team and chip integration.

#WEAREIPG

• IMPORTANT:  Please be informed that Intel is proactively trying to find candidates for a backend engineer position which is frequently available at Intel.  Please note that the position may not be available at this time. If you would be interested in this position should it become available, we would encourage you to apply, and our hiring team will be glad to contact you when/if relevant.”

Qualifications

BSc. in EE or equivalent

3+ years of hands on experience in backend design

scripting capabilities is an advantage

Knowledge of synopsys advanced implementation and verification tool

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.