Title：2019 Synopsys 中国实习生计划 (2019 Synopsys China Internship Program)

Location： Shanghai/ Wuhan

简历请投递至：campus@synopsys.com

可供开放的暑期实习项目 （Available Projects）：

1. Timing Analysis Automation for ASIC Backend Design

2. Integrated Testing Environment Development

3. Simulation Window for Dynamic Timing Analysis and Validation

4. Synthesizer Feature Development on Emulation Tool

5. White Box Test for Graph Theory - Algorithm Research

6. Compiler Enhancement for VCS (Verilog compiler) Incremental

7. Machine Learning applying on Physical Synthesis tool

More……

要求：

1. 在校研究生或本科生，在读计算机工程、软件工程、电子\通讯等或相关专业

2. 具备敏捷的学习能力，较强的技术分析和解决问题的能力

3. 有一定的技术描述和表达能力，善于和团队交流和相互学习

4. 具备以下任何一项或多项技能：

• 熟悉在 Unix/Linux 平台且有C++ programming的经验

• 或，熟悉脚本语言Python, Shell, TCL，或一定运用实践经验等

• 或，了解建模、大数据处理、图论、算法、机器学习基本知识或相关实践经验

• 或，熟悉Verilog HD 或有 programming 的经验

• 或，熟悉ASIC前端/后端设计流程 和 基本验证方法论
  

Requirements：

1. Currently on Master and PhD study , the major is in Computer engineering, Computer Science/Software engineering or Electronic / Telecommunication Engineering or relevance

2. Agile learning capability, Good analysis and Problem solving skills

3. Can explicitly present technical issues and can be willing to communicate and interact with people in the team

4. Be skillful in one or more of the following fields:

- C++ programming development experience on Unix/Linux

• Or, Script experience via Python, Shell or TCL, etc.

• Or, Basic knowledge of modeling, big data, graph theory, algorithms and machine Learning

- Or, have the programing experiences or knowledge on Verilog HDL

• Or,,Basic knowledge of ASIC Frontend/Backend design flow &verification methodology

上班地址：上海市长宁区长宁路1027号兆丰广场