Principal Duties and Responsibilities:

(1) Working on digital IC design/verification;

(2) Responsible for RTL design & simulation, pre-/post-layout simulation, assist system team for FPGA verification.

(3) Responsible for digital signal processor RTL design and verification

(4) Responsible for 8/32bits Microcontroller design, and AXI/AHB/APB system bus design

(5) Cooperating with analog/RF/System/Algorithm team

Knowledge, Skills, and Abilities Required:

(1) BS Degree or above in EE or equivalent;

(2) Proficient in Verilog

(3) Familiar with ASIC design flow and IC design tools such as VCS, Design Compiler, Prime Time etc.;

(4) Familiar with script languages Perl,TCL,SHELL etc.;

(5) Experience of digital signal processing design is preferred;

(6) Programming skills in SystemVerilog/UVM verification methodology is preferred

(7) Low power design/verification experience (Multi-Voltage, power gating, UPF/CPF and etc.) is a plus

(8) Experience on FPGA verification is a plus

(9) Knowledge of communication interfaces such as I2C, SMBUS, SPI, UART is a plus;

(10) Experience of logic synthesis, formal verification, static timing analysis, DFT is a plus.

(11) Have successfully experience of tape out;

(12) Good oral and written English communication skills;

(13) Creative, self-motivated, responsible, good team work spirit.

(14) Fresh graduate but smart and fast-learning are also welcome!

上班地址：高新区