职责描述：

1. Run schematic and layout simulations using tools like Spectre, HSPICE, AFS;

2. Perform analog simulations like noise analysis, loop stability, ac/dc/tran, monte-carlo analysis;

3. Work with circuit design engineers and system architects to write test plans, present results, and communicate clearly with designers and project leader;

4. Execute and develop verification workflows for design sign-off;

任职要求：

1.Engineering degree in an electronic or microelectronic field and 2+ years working experience in integrated circuits design or verification.

2. Understanding of basic analog building blocks and mixed signal blocks;

3. Hands on experience in Cadence Virtuoso tools;

4. Experience with behavioral modeling languages (Verilog, Verilog-A, Verilog-AMS, System Verilog) is a strong plus.

5. Experience with scripting languages like Python, PERL, TCL is a plus.

其他：

1. Good team player, attitude and thirst for continuous learning

2. Strong communication and interpersonal skills

3. Ability to function independently, be self-driven

上班地址：上海浦东软件园祖冲之园